Reduction in transistor size has been accompanied by a higher degree of integration in semiconductor integrated circuits and by continuing improvements in the speed at which electrical signals are processed. In relation to signal transmission by electrical interconnects (wiring traces) in a semiconductor integrated circuit, and in particular with regard to global interconnects, which are comparatively long-haul interconnects within the chip, problems such as wiring delay, signal skew (a difference in reception times) and jitter (fluctuation) are arising. Further problems are signal degradation due to crosstalk between adjacent electrical interconnects and the effects of electromagnetic noise from the surroundings of the semiconductor integrated circuit.
Techniques for substituting an optical interconnect structure for some of the electrical interconnects of a semiconductor integrated circuit continue to be developed as method of solving the above-mentioned problems. A method of fabrication in which an optical interconnect layer formed on a substrate separate from a semiconductor integrated circuit is bonded to an electrical interconnect layer has been proposed as such a technique.
For example, Non-Patent Document 1 discloses forming a semiconductor integrated circuit composed of transistors or the like on a semiconductor substrate made of Si or the like, on the other hand forming an optical interconnect layer incorporating a waveguide and a transceiver element, etc., forming pads for electrical connections on respective ones of the side on which the semiconductor integrated circuit has been formed and the side of the optical interconnects, and forming a final device by electrically connecting between the pads.
Further, Patent Document 1 discloses ones obtained by implementing an interlayer connection, through use of interlayer vias, between a semiconductor chip mounted on a first main surface of a resin layer and an optical chip embedded in a second main surface of the resin layer. A connection terminals and bumps are formed on the optical chip on the surface thereof facing the side of the optical chip, and the opposite side (the underside) has no connection terminal. As a result, it is disclosed that since the semiconductor chip and the optical chip are connected over a short distance, parasitic capacitance, which is produced by the connection between the semiconductor chip and the optical chip, can be reduced.